- Each target signifies a file to be updated.
- If a target is included as a command-line argument, that target is updated.
- The default goal, first target in the file
- other goal if specified at command line
gcc hello.c -o hello
target1 target2 target3 : prerequisite1 prerequisite2
- This "chaining" of targets to prerequisites to targets to prerequisites is typical of how make analyzes a makefile to decide the commands to be performed.
- The -l option to gcc indicates a system library that must be linked into the application. GNU make includes special support for this syntax. When a prerequisite of the form -l<NAME> is seen, make searches for a file of the form libNAME.so; if no match is found, it then searches for libNAME.a.
- Each command must begin with a tab character. This (obscure) syntax tells make that the characters that follow the tab are to be passed to a subshell for execution.
- A # indicates comment
- When asked to update a target, make will execute the command script of the rule if any of the prerequisite files has been modified more recently than the target.
- the following two snippets are equivalent
target1 target2: prereq1 prereq2 prereq3
target1: prereq1 prereq2 prereq3
target2: prereq1 prereq2 prereq3
- a label representing a command script- shell scripts embedded in a makefile.
- Any target can be declared phony by including it as a prerequisite of .PHONY:
- Phony targets are always out of date
- Standard phony targets:
- all = Perform all tasks to build the application
- install = Create an installation of the application from the compiled binaries
- clean = Delete the binary files generated from sources
- distclean = Delete all the generated files that were not in the original source distribution
- TAGS = Create a tags table for use by editors
- check = Run any tests associated with this application
- indicate a specific target to be updated if it is out of date with respect to any of its prerequisites.
- replaces the obsolete "suffix" rules
- use wildcards instead of explicit filenames. This allows make to apply the rule any time a target file matching the pattern needs to updated.
- identical to the Bourne shell's
- ~, *, ?, [...], and [^...].
- A question mark represents any single character, ** [...] represents a character class
- (negated) character class use [^...]
- Wildcard in target or prerequisite = expansion by make
- However, when the pattern appears in a command, the expansion is performed by the subshell.
- Percent character in a pattern rule is roughly equivalent to * in a Unix shell
- The three built-in rules
$(COMPILE.c) $(OUTPUT_OPTION) $<
$(LEX.l) $< > $@
$(LINK.c) $^ $(LOADLIBES) $(LDLIBS) -o $@
- Rules database built-in to make
Static pattern rules
- like regular pattern rules except they apply only to a specific list of target files.
command line options
- —just-print, -n = tells make to display the commands it would execute for a particular target without actually executing them
- —print-data-base = look at make's default set of rules (and variables)
- syntax = $(variable-name)
- COMPILE.c = variable containing the C compile command
- VPATH = A list of directories to search when make needs a file.
- Searched for targets as well as prerequisites, but not for files mentioned in command scripts.
- Separated by spaces.
- lowercase vpath used to specify places for certain types of files
vpath %.c src
vpath %.h include
- Single character variable name does not require the parentheses
- $@ = The filename representing the target.
- $% = The filename element of an archive member specification.
- $< = The filename of the first prerequisite.
- $? = The names of all prerequisites that are newer than the target, separated by spaces.
- $^ = The filenames of all the prerequisites, separated by spaces, duplicates removed.
- $+ = Same as $^, but includes duplicates.
- $* = The stem of the target filename, typically a filename without its suffix.